With the recent surge in the demand for lab-on-chip applications, the requirement for a low-cost integration of different technologies, in particular CMOS/MEMS and microfluidics has become crucial. Economies-of-scale especially driven by the semiconductor industry favour solutions based on unmodified commercial processes. The constraints dictated by the varying range of physical dimensions of the different components make wafer-level integration too costly for low-cost mass manufacture. For example, a typical lab-on-chip application may require CMOS components of area in the region of 1-10 sq. mm, MEMS components in the region of 25-100 sq. mm and microfluidics components in the region of 200-2500 sq. mm. Therefore integrating these at wafer level would be hugely wasteful to CMOS/MEMS technologies, as the common lab-on-chip area would be constrained by the requirement of interfacing fluids and external systems to the devices. A common technique for integrating these components at die-level, for example in chemical sensing, includes the following sequence. Wire bonding the chip to a package or substrate, encapsulating the wire bonds in an insulating material, levelling off the top surface, patterning the sensing regions (on chip surface) through the encapsulant, and finally aligning and laying on the microfluidics layers. The main challenges to this approach are all related to the fact that the bond wires are protruding above the sensing surface. In addition to this resulting in crucial reliability issues, the surface geometry is vastly affected, i.e. unwanted wells are created inside the bond pad regions and, the top surface (above the encapsulant) is far from planar- resulting in sealing and thus reliability issues when overlaying the microfluidics. A novel solution to this integration problem is proposed here. The idea is to develop a methodology for interfacing to CMOS chips without any bond wires such that the top chip surface is left planar with no bondpad openings. The challenge is therefore to develop a technique to: (1) provide power and control signals to a CMOS chip and (2) communicate data from the CMOS chip to an external device in a contactless fashion. Furthermore, an added challenge of having no off-chip connections is that no off-chip components, for example, antennas or capacitors can be used- such as in the case of RFID's. We therefore propose to apply optical techniques in a hybrid PCB/CMOS assembly such that the top surface is left virtually planar with all external components being mounted underneath the CMOS die. The scheme intends to supply power and control via an infrared (IR) emitter through the silicon using a relatively large area deep well photodiode to recover power and data. The transmitted light (i.e. non-absorbed photons) can therefore be modulated using electro-optical effects and reflected back through the die to a detector mounted beneath the CMOS die. The data can therefore be extracted from the received signal using relatively simple discrete electronics. Although this scheme is initially intended for hybrid, lab-on-chip applications, the wider scope for exploitation is enormous, with an impacting application-base throughout the microelectronics industry.