Energy efficiency is one of the primary design constraints for modern processing systems. Limited battery life and excessive internal power densities limit the number of transistors that can be active simultaneous in a silicon chip. Energy and power reduction in conventional computing is limited by the inability of modifying the architecture or adapting to changes in the fabrication process, temperature or application requirements after chip fabrication. When these changes are possible are limited by the need of "margining" that introduces safety margins so devices operate under worst conditions. Worst conditions are rarely the case an important energy and performance gains are possible if technology can adapt to the real conditions of operation. This research addresses this challenge by investigating energy proportional computing with a novel voltage, frequency and logic scaling triplet to adapt to changes in applications, fabrication or operating conditions. The results from this research are expected to deliver new fundamental insights to the question of: How future computers can obtain orders of magnitude higher performance with limited energy budgets?