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[{"model": "core.projectfund", "pk": 26756, "fields": {"project": 3946, "organisation": 4, "amount": 249982, "start_date": "2015-09-30", "end_date": "2017-09-29", "raw_data": 42501}}]
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| Jan. 28, 2023, 11:08 a.m. |
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[{"model": "core.projectperson", "pk": 54098, "fields": {"project": 3946, "person": 11084, "role": "PM_PER"}}]
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| Jan. 28, 2023, 10:52 a.m. |
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{"external_links": []}
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| April 11, 2022, 3:46 a.m. |
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[{"model": "core.projectfund", "pk": 18861, "fields": {"project": 3946, "organisation": 4, "amount": 249982, "start_date": "2015-09-30", "end_date": "2017-09-29", "raw_data": 18684}}]
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| April 11, 2022, 3:46 a.m. |
Created
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[{"model": "core.projectorganisation", "pk": 72117, "fields": {"project": 3946, "organisation": 3069, "role": "PARTICIPANT_ORG"}}]
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| April 11, 2022, 3:46 a.m. |
Created
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[{"model": "core.projectorganisation", "pk": 72116, "fields": {"project": 3946, "organisation": 3069, "role": "LEAD_ORG"}}]
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| April 11, 2022, 3:46 a.m. |
Created
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[{"model": "core.projectperson", "pk": 44330, "fields": {"project": 3946, "person": 5835, "role": "PM_PER"}}]
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| April 11, 2022, 1:47 a.m. |
Updated
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{"title": ["", "State-of-the-Art Low Power Memory for Battery Powered Applications"], "description": ["", "\nThe crux of this application is to develop extremely low power, working samples of CMOS\nmemory \u2018chips\u2019 suitable for customer evaluation on the latest 40nm Low Power process\n(40ULP) available from the leading global silicon foundry, TSMC. SureCore have already\nproven their power reducing concepts save up to 60% active power compared with 6 rival\nsolutions in an independent test. The new 40ULP process released by TSMC has been\nspecifically developed for portable, mobile, wearable, and energy scavenging products where\nbattery life is key. The objective for SureCore is to become a leading vendor of Static\nRandom Access Memory (SRAM) IP for integration into System on Chip (SoC) devices by\nsemiconductor product suppliers. In order to achieve this, the power saving techniques must\nbe proven on real silicon on the target process. This is the purpose of this application.\nSRAM memory is a key IP block essential to the development of SoC devices found in the\nmajority of modern electronic products and will occupy up to 70% of SoC silicon area by\n2017. This growth is driven by consumer demand for more features integrated into their\nmobile devices. However battery technology continues to lag consumer expectations;\nintegrating more functionality means more memory which can consume up to 70% of battery\npower when active. The industry\u2019s approach to date has been to reduce battery voltage but this\napproach has reached the end of the road; a rethink of the memory architecture is required.\nThe secret of SureCore\u2019s power saving technology is a re-design of the internal memory\narchitecture without changing the external interfaces and with minimal change in\nperformance.\nSureCore\u2019s low power memory technology has attracted the attention of many global\nsemiconductor companies who have expressed commercial interest if the benefits can be\nproven on the new 40ULP process. This project would achieve that, moving the company\nforward towards establishing commercial agreements.\n\n"], "extra_text": ["", "\n\n\n\n"], "status": ["", "Closed"]}
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| April 11, 2022, 1:47 a.m. |
Added
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{"external_links": [15229]}
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| April 11, 2022, 1:47 a.m. |
Created
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[{"model": "core.project", "pk": 3946, "fields": {"owner": null, "is_locked": false, "coped_id": "a810cfc4-159a-4668-aaa5-05f9340f130c", "title": "", "description": "", "extra_text": "", "status": "", "start": null, "end": null, "raw_data": 18670, "created": "2022-04-11T01:37:37.639Z", "modified": "2022-04-11T01:37:37.639Z", "external_links": []}}]
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