The crux of this application is to develop extremely low power, working samples of CMOS
memory ‘chips’ suitable for customer evaluation on the latest 40nm Low Power process
(40ULP) available from the leading global silicon foundry, TSMC. SureCore have already
proven their power reducing concepts save up to 60% active power compared with 6 rival
solutions in an independent test. The new 40ULP process released by TSMC has been
specifically developed for portable, mobile, wearable, and energy scavenging products where
battery life is key. The objective for SureCore is to become a leading vendor of Static
Random Access Memory (SRAM) IP for integration into System on Chip (SoC) devices by
semiconductor product suppliers. In order to achieve this, the power saving techniques must
be proven on real silicon on the target process. This is the purpose of this application.
SRAM memory is a key IP block essential to the development of SoC devices found in the
majority of modern electronic products and will occupy up to 70% of SoC silicon area by
2017. This growth is driven by consumer demand for more features integrated into their
mobile devices. However battery technology continues to lag consumer expectations;
integrating more functionality means more memory which can consume up to 70% of battery
power when active. The industry’s approach to date has been to reduce battery voltage but this
approach has reached the end of the road; a rethink of the memory architecture is required.
The secret of SureCore’s power saving technology is a re-design of the internal memory
architecture without changing the external interfaces and with minimal change in
performance.
SureCore’s low power memory technology has attracted the attention of many global
semiconductor companies who have expressed commercial interest if the benefits can be
proven on the new 40ULP process. This project would achieve that, moving the company
forward towards establishing commercial agreements.