The rapid acceleration of technological improvement over the last half century, particularly computing power, is largely down to the improvements in transistor technology. These traditional transistors, those that use silicon dioxide are engineered at the nanometre level, are at the threshold of their economic viability: smaller devices of this type would lead to dramatic increase of power consumption for a diminishingly small return in computing capability. It is for this reason that attention has been paid to new high-k dielectric materials to replace the silicon dioxide; furthermore, silicon has been considered to be replaced by gallium nitride (GaN) and silicon carbide (SiC) for power electronics applications. An opportunity to significantly lower the global energy consumption is by increasing the efficiency of power electronics technology. Power electronics are crucial to maximizing the efficiency of high voltage transmission lines and improving the battery life of a mobile phone. They are found in railways, in TVs, in energy efficient lighting. The traditional electronic devices that control these systems are silicon-based transistors. This project will focus on developing wide band gap (GaN, SiC) semiconductor devices to generate a route that reduces power consumption and cost of the devices. A considerably larger band gap (~3 eV) than silicon (1.1 eV), permits devices to operate at high temperatures and voltages, making power electronic modules that use these materials significantly more efficient. The ability to withstand high temperatures can minimize the additional costs and components required to prevent devices from overheating.
While high-k materials provide an avenue for further enhancements of HEMT and MOSFET technology, they require careful engineering with the semiconductor substrate, particularly at the interface. The goal of this project is to examine these interfaces, through physical characterisation techniques, and assess their viability for transistor technology using electrical characterisation techniques. Techniques such as X-ray Photoelectron Spectroscopy (XPS) and spectroscopic ellipsometry (SE) will be used to probe the properties of the high-k dielectric/semiconductor interface, while capacitance voltage (C-V) and current voltage (I-V) as well as resistivity measurements will give insight into the electrical properties of the stacks. These measurements will be performed on stacks fabricated in house, using atomic layer deposition and sputtering techniques.
This project will focus on investigation of nanolaminate dielectrics, in particular optimal dopants (such as scandium, titanium) in Al2O3 thin film matrix for inclusion into GaN enhancement (E)-mode HEMTs. The latter has not been demonstrated with the required reliability for commercial applications and present a major research opportunity. Fabricating nanolaminates with tailored composition can achieve desired trade-offs in terms of high-dielectric constant (k) and band offsets leading to superior performance in HEMT devices. Al2O3 has been used in GaN HEMTs but suffers small k of ~10; doping it, for example with Sc (whose oxide configuration has k of ~26) can achieve a dielectric with a wide band gap >6 eV and a high-k. Furthermore, much attention has also been paid to GaN nanostructures because nanoscale materials, such as nanowires, nanotubes, and nanorods, are dislocation-free and strain-free with large surface area-to-volume ratios. Due to these characteristics, GaN nanostructures have the potential to exhibit superior performance to conventional planar GaN. In this project, differing GaN phases (including planar, nanowires and nano-networks) will be studied to understand their material properties and the role of oxide formation at the interface.