The integrated circuit (IC) industry has been rapidly and consistently scaling the design rules and improving the design of devices and circuits for over 35 years. As a result, the semiconductor industry has enjoyed exponential increase in chip speed and functional density with time, combined with an exponential decrease in power dissipation and cost per function, as projected by Moore's Law. However, the industry is facing increasing difficulties in continuing to scale down fully depleted MOSFETs to nanoscale dimensions owing to certain key device, material and process limits such as intrinsic parameter fluctuations, increased short channel effects (SCEs), increased parasitic series resistance and fabrication of thin defect free silicon film. To overcome these limitations, multiple gate devices (MuGFETs) have been proposed, where the requirement of using ultra thin silicon film is relaxed due to efficient gate control that enhances short channel immunity. The FinFET is a particularly popular MuGFET in which current flows horizontally (parallel to the plane of the substrate) between the source and drain, along opposite vertical channel surfaces. A lithographically defined gate straddles the fin, forming self-aligned, electrically connected gate electrodes along the sidewalls of the fin.Novel nanoscale 3D MOS structures require non-classical distinctive effects such as non vertical sidewalls, non self-aligned gates, corner effects, quantum effects, source/drain (S/D) extension region engineering, intrinsic and extrinsic parasitic resistances and capacitances, to be accurately modelled and simulated to understand and optimise the device structure. Traditional assumptions for idealised devices ignore these highly dominant non-classical distinctive effects that critically govern the behaviour of MuGFETs in the nanoscale regime. These effects must be accurately simulated in order to assess the advantages and challenges of MuGFETs for digital, analog and high frequency applications. The proposed research will provide an understanding of the performance of these devices by means of comprehensive physical device simulations including intrinsic and extrinsic parameters, detailed broadband experimental characterisation and parameter extraction techniques as well as provide solutions to the semiconductor industry for devices at the end of ITRS roadmap and beyond. The final outcome will be 3D parameterised simulation of nanoscale MuGFETs with inclusion of all relevant intrinsic and extrinsic parasitics, improved physical models for carrier transport and the assessment of new channel materials and gate dielectrics for static and dynamic applications. The work will be carried out at Northern Ireland Semiconductor Research Centre, Queen's University Belfast and linked its ongoing experimental research projects on silicides, metal gate and high-k dielectrics. The project will carried out in collaboration with Institute of Microelectronics, Electromagnetism and Photonics, France, ATMEL North Tyneside, UK, Universit catholique de Louvain, Belgium and National Semiconductor USA.