Multi-layered ceramic capacitors (MLCCs) are the foundation of the electronics (passive components) industry. Each layer within a MLCC is created by sintering a power, typically a chemically-doped, functional oxide such as Barium Titanate. This processing route generates a complex microstructure that can include grains, grain-boundaries, pores, interface roughness and graded material properties. Many of these microstructural effects are known to influence device performance but the knowledge of their exact mechanism and strength of their effect is limited. The current favoured approach towards optimising these effects is based on trial and error experimentation; however, this is challenging and time and resource consuming. Here we shall be studying such microstructural phenomena using both experimental and finite element modelling methods in order to provide a resource efficient, controlled and systematic approach towards a faster route for optimisation of current materials and devices.